Stockfish Testing Queue

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Finished - 2276 tests

14-12-17 Vo fmcT2 diff
LLR: -2.94 (-2.94,2.94) [0.00,4.00]
Total: 22356 W: 3979 L: 4059 D: 14318
sprt @ 10+0.1 th 1 take 2
12-12-17 Vo fmcT diff
LLR: -2.95 (-2.94,2.94) [0.00,4.00]
Total: 77633 W: 14161 L: 14052 D: 49420
sprt @ 10+0.1 th 1 moveCount formula tweak...
12-12-17 Vo seLMR diff
LLR: -2.95 (-2.94,2.94) [0.00,5.00]
Total: 19853 W: 3628 L: 3668 D: 12557
sprt @ 10+0.1 th 1 take 2
12-12-17 Vo cutNodeLmr diff
LLR: -2.95 (-2.94,2.94) [0.00,5.00]
Total: 25659 W: 4598 L: 4614 D: 16447
sprt @ 10+0.1 th 1 stc
11-12-17 Vo seLMR diff
LLR: -2.96 (-2.94,2.94) [0.00,5.00]
Total: 20408 W: 3633 L: 3672 D: 13103
sprt @ 10+0.1 th 1 stc
10-12-17 Vo lmrt4 diff
LLR: -2.95 (-2.94,2.94) [0.00,5.00]
Total: 8190 W: 1441 L: 1531 D: 5218
sprt @ 10+0.1 th 1 stc
09-12-17 Vo ttCaptureLMR diff
LLR: -2.95 (-2.94,2.94) [0.00,5.00]
Total: 45560 W: 8263 L: 8194 D: 29103
sprt @ 10+0.1 th 1 stc
10-12-17 Vo ttExact diff
LLR: -2.96 (-2.94,2.94) [0.00,4.00]
Total: 25680 W: 3187 L: 3269 D: 19224
sprt @ 60+0.6 th 1 Use [0, 4] bounds...per Marco's request.
09-12-17 Vo captureSeriesLMR diff
LLR: -2.95 (-2.94,2.94) [0.00,5.00]
Total: 6365 W: 1113 L: 1211 D: 4041
sprt @ 10+0.1 th 1 stc
09-12-17 Vo ttExactLMR diff
LLR: -2.96 (-2.94,2.94) [0.00,5.00]
Total: 26837 W: 4867 L: 4878 D: 17092
sprt @ 10+0.1 th 1 Test this against passed ttExact patch...
09-12-17 Vo lmrt3b diff
LLR: -2.96 (-2.94,2.94) [0.00,5.00]
Total: 20896 W: 3723 L: 3760 D: 13413
sprt @ 10+0.1 th 1 ver 3b
08-12-17 Vo lmrt2 diff
LLR: -2.96 (-2.94,2.94) [0.00,5.00]
Total: 26831 W: 4943 L: 4953 D: 16935
sprt @ 10+0.1 th 1 take 2
08-12-17 Vo lmrt3 diff
LLR: -2.97 (-2.94,2.94) [0.00,5.00]
Total: 24082 W: 4272 L: 4296 D: 15514
sprt @ 10+0.1 th 1 ver 3
08-12-17 Vo lmrT diff
LLR: -2.96 (-2.94,2.94) [0.00,5.00]
Total: 66951 W: 12071 L: 11913 D: 42967
sprt @ 10+0.1 th 1 stc
06-12-17 Vo pvExactExp diff
LLR: 2.95 (-2.94,2.94) [-3.00,1.00]
Total: 75161 W: 9548 L: 9497 D: 56116
sprt @ 60+0.6 th 1 LTC: Suggested to use simplified bounds.
04-12-17 Vo pvExactExp diff
LLR: 2.95 (-2.94,2.94) [0.00,4.00]
Total: 110053 W: 20233 L: 19700 D: 70120
sprt @ 10+0.1 th 1 See how this goes...
05-12-17 Vo lmrRand diff
LLR: -2.96 (-2.94,2.94) [0.00,5.00]
Total: 4320 W: 721 L: 828 D: 2771
sprt @ 10+0.1 th 1 Fixed...
05-12-17 Vo ttExp diff
LLR: -1.50 (-2.94,2.94) [0.00,5.00]
Total: 2257 W: 383 L: 437 D: 1437
sprt @ 10+0.1 th 1 stc
04-12-17 Vo checkExtT diff
LLR: -2.95 (-2.94,2.94) [0.00,5.00]
Total: 6384 W: 1105 L: 1203 D: 4076
sprt @ 10+0.1 th 1 stc
04-12-17 Vo inCheckIID diff
LLR: -2.95 (-2.94,2.94) [0.00,5.00]
Total: 15861 W: 2794 L: 2852 D: 10215
sprt @ 10+0.1 th 1 Fixed patch...
04-12-17 Vo inCheckIID diff
LLR: -0.94 (-2.94,2.94) [0.00,5.00]
Total: 1211 W: 210 L: 245 D: 756
sprt @ 10+0.1 th 1 Allow IID if inCheck
03-12-17 Vo SEgivesCheck diff
LLR: -2.96 (-2.94,2.94) [0.00,5.00]
Total: 15245 W: 2798 L: 2858 D: 9589
sprt @ 10+0.1 th 1 Don't do SE if giving check....
02-12-17 Vo ttCaptureSP diff
LLR: -2.95 (-2.94,2.94) [0.00,5.00]
Total: 7022 W: 1218 L: 1313 D: 4491
sprt @ 10+0.1 th 1 stc
02-12-17 Vo ttCaptureSP2 diff
LLR: -2.95 (-2.94,2.94) [0.00,5.00]
Total: 17999 W: 3188 L: 3237 D: 11574
sprt @ 10+0.1 th 1 What I originally wanted to do...
01-12-17 Vo kpst diff
LLR: -2.95 (-2.94,2.94) [0.00,4.00]
Total: 66411 W: 11931 L: 11862 D: 42618
sprt @ 10+0.1 th 1 stc
30-11-17 Vo supportedDouble diff
LLR: -2.94 (-2.94,2.94) [0.00,5.00]
Total: 13828 W: 2459 L: 2525 D: 8844
sprt @ 10+0.1 th 1 stc
30-11-17 Vo doubleRedefine' diff
LLR: -2.97 (-2.94,2.94) [0.00,5.00]
Total: 9798 W: 1733 L: 1817 D: 6248
sprt @ 10+0.1 th 1 Hopefully this will fix it...
30-11-17 Vo doubleIsolated diff
LLR: -2.95 (-2.94,2.94) [0.00,5.00]
Total: 5132 W: 862 L: 965 D: 3305
sprt @ 10+0.1 th 1 Last try
30-11-17 Vo doubleIsolated diff
LLR: -2.96 (-2.94,2.94) [0.00,5.00]
Total: 13885 W: 2507 L: 2573 D: 8805
sprt @ 10+0.1 th 1 take 2
30-11-17 Vo doubleIsolated diff
LLR: -2.96 (-2.94,2.94) [0.00,5.00]
Total: 73932 W: 13423 L: 13234 D: 47275
sprt @ 10+0.1 th 1 Compound penalty if pawn is both isolated and doubled.
29-11-17 Vo sortingSpeedup diff
LLR: -2.95 (-2.94,2.94) [0.00,4.00]
Total: 53919 W: 9715 L: 9688 D: 34516
sprt @ 10+0.1 th 1 Use the correct bounds for this "free" non-functional speedup... if passes I will submit a pull request.
29-11-17 Vo isolated diff
LLR: -2.95 (-2.94,2.94) [0.00,5.00]
Total: 8707 W: 1533 L: 1621 D: 5553
sprt @ 10+0.1 th 1 Isolated Pawn penalty based by file.
28-11-17 Vo hthSpeedup diff
LLR: -2.96 (-2.94,2.94) [0.00,5.00]
Total: 11238 W: 1936 L: 2014 D: 7288
sprt @ 10+0.1 th 1 Hacked to Hell speedup attempt.
28-11-17 Vo fullSortNearRoot diff
LLR: -2.95 (-2.94,2.94) [0.00,5.00]
Total: 11088 W: 1929 L: 2007 D: 7152
sprt @ 10+0.1 th 1 stc
28-11-17 Vo sortingCutNode diff
LLR: -2.95 (-2.94,2.94) [0.00,5.00]
Total: 19002 W: 3414 L: 3458 D: 12130
sprt @ 10+0.1 th 1 stc
27-11-17 Vo sortingSpeedup diff
LLR: -2.96 (-2.94,2.94) [0.00,5.00]
Total: 52066 W: 9491 L: 9394 D: 33181
sprt @ 10+0.1 th 1 If skipQuiet is already triggered we can increase the margin to 0 for sorting quiets...giving us a speedup with no change in functionality.
27-11-17 Vo pvExactQuietGen diff
LLR: -2.95 (-2.94,2.94) [0.00,5.00]
Total: 22518 W: 4056 L: 4085 D: 14377
sprt @ 10+0.1 th 1 Higher margin for sorting quiets at pvExact nodes
26-11-17 Vo lmrTweak diff
LLR: -2.41 (-2.94,2.94) [0.00,5.00]
Total: 89829 W: 16449 L: 16167 D: 57213
sprt @ 10+0.1 th 1 take 2
26-11-17 Vo lmrTweak diff
LLR: -2.96 (-2.94,2.94) [0.00,5.00]
Total: 10551 W: 1299 L: 1383 D: 7869
sprt @ 60+0.6 th 1 Would like to get an idea of how this yellow patch scale...(low thoughtput)
25-11-17 Vo lmrTweak diff
LLR: -2.95 (-2.94,2.94) [0.00,5.00]
Total: 32846 W: 5866 L: 5852 D: 21128
sprt @ 10+0.1 th 1 stc
25-11-17 Vo redT3 diff
LLR: -2.96 (-2.94,2.94) [0.00,5.00]
Total: 9967 W: 1755 L: 1838 D: 6374
sprt @ 10+0.1 th 1 stc
25-11-17 Vo mcpT2 diff
LLR: -2.95 (-2.94,2.94) [0.00,5.00]
Total: 23162 W: 4118 L: 4145 D: 14899
sprt @ 10+0.1 th 1 ver 2
25-11-17 Vo mcpT diff
LLR: -2.96 (-2.94,2.94) [0.00,5.00]
Total: 9066 W: 1618 L: 1705 D: 5743
sprt @ 10+0.1 th 1 stc
25-11-17 Vo impT2 diff
LLR: -2.96 (-2.94,2.94) [0.00,4.00]
Total: 14310 W: 2536 L: 2644 D: 9130
sprt @ 10+0.1 th 1 ver 2
24-11-17 Vo impT diff
LLR: -2.94 (-2.94,2.94) [0.00,5.00]
Total: 25376 W: 3156 L: 3193 D: 19027
sprt @ 60+0.6 th 1 ltc
24-11-17 Vo redExp2 diff
LLR: -2.96 (-2.94,2.94) [0.00,5.00]
Total: 13454 W: 2417 L: 2485 D: 8552
sprt @ 10+0.1 th 1 stc
24-11-17 Vo impT diff
LLR: 2.96 (-2.94,2.94) [0.00,5.00]
Total: 7185 W: 1375 L: 1219 D: 4591
sprt @ 10+0.1 th 1 stc
23-11-17 Vo redExp diff
LLR: -2.95 (-2.94,2.94) [0.00,5.00]
Total: 34073 W: 6146 L: 6126 D: 21801
sprt @ 10+0.1 th 1 stc
23-11-17 Vo failLowLMR2 diff
LLR: -2.95 (-2.94,2.94) [0.00,5.00]
Total: 13261 W: 2308 L: 2377 D: 8576
sprt @ 10+0.1 th 1 Take 2
23-11-17 Vo failLowLMR diff
LLR: -2.96 (-2.94,2.94) [0.00,5.00]
Total: 5278 W: 910 L: 1013 D: 3355
sprt @ 10+0.1 th 1 Don't do LMR at rootNodes if prior move(s) failed low...