Stockfish Testing Queue

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Finished - 220 tests

24-05-17 vd races3 diff
LLR: 2.96 (-2.94,2.94) [-3.00,1.00]
Total: 169597 W: 29938 L: 30066 D: 109593
sprt @ 5+0.05 th 3 a third approach to fix races. Test for no regression
22-05-17 vd races32 diff
LLR: 2.94 (-2.94,2.94) [-3.00,1.00]
Total: 130122 W: 22862 L: 22924 D: 84336
sprt @ 5+0.05 th 3 check for no regression, split 32 and 64 bit treatment
20-05-17 vd races diff
LLR: -2.96 (-2.94,2.94) [-3.00,1.00]
Total: 38209 W: 6642 L: 6862 D: 24705
sprt @ 5+0.05 th 3 check for no regression
18-05-17 vd races diff
LLR: -2.96 (-2.94,2.94) [-3.00,1.00]
Total: 51262 W: 8857 L: 9098 D: 33307
sprt @ 5+0.05 th 3 check for no regression in threaded case.
14-05-17 vd cmhv2 diff
LLR: 2.97 (-2.94,2.94) [-3.00,1.00]
Total: 174175 W: 31503 L: 31643 D: 111029
sprt @ 10+0.1 th 1 test for no regression.
13-05-17 vd master diff
LLR: 2.53 (-2.94,2.94) [0.00,4.00]
Total: 51615 W: 9542 L: 9231 D: 32842
sprt @ 10+0.1 th 1 0.2% slowdown
13-05-17 vd master diff
LLR: 2.95 (-2.94,2.94) [0.00,4.00]
Total: 23353 W: 4420 L: 4182 D: 14751
sprt @ 10+0.1 th 1 0.3% slowdown ... !?
13-05-17 vd master diff
LLR: 2.95 (-2.94,2.94) [0.00,4.00]
Total: 20542 W: 3801 L: 3575 D: 13166
sprt @ 10+0.1 th 1 0.5% slowdown
13-05-17 vd master diff
LLR: 2.95 (-2.94,2.94) [0.00,4.00]
Total: 15692 W: 2872 L: 2664 D: 10156
sprt @ 10+0.1 th 1 0.7% slowdown
13-05-17 vd master diff
LLR: 2.95 (-2.94,2.94) [0.00,4.00]
Total: 7906 W: 1518 L: 1335 D: 5053
sprt @ 10+0.1 th 1 slowdown 1%
13-05-17 vd master diff
LLR: 2.95 (-2.94,2.94) [0.00,4.00]
Total: 6865 W: 1333 L: 1153 D: 4379
sprt @ 10+0.1 th 1 slowdown 1.5%
12-05-17 vd int16v3 diff
LLR: -2.94 (-2.94,2.94) [0.00,4.00]
Total: 62608 W: 11312 L: 11255 D: 40041
sprt @ 10+0.1 th 1 as requested in PR #1113
10-05-17 vd int16 diff
LLR: 2.95 (-2.94,2.94) [-3.00,1.00]
Total: 54476 W: 9949 L: 9886 D: 34641
sprt @ 10+0.1 th 1 stc (just test the int16 bit for no regression).
11-05-17 vd int16v2 diff
LLR: 2.96 (-2.94,2.94) [-3.00,1.00]
Total: 27019 W: 4905 L: 4794 D: 17320
sprt @ 10+0.1 th 1 take 2
10-05-17 vd tosq diff
LLR: -2.96 (-2.94,2.94) [0.00,5.00]
Total: 8621 W: 1499 L: 1588 D: 5534
sprt @ 10+0.1 th 1 stc
10-05-17 vd fromto diff
LLR: -2.97 (-2.94,2.94) [0.00,5.00]
Total: 2946 W: 470 L: 583 D: 1893
sprt @ 10+0.1 th 1 stc
08-05-17 vd threading2 diff
ELO: -4.69 +-8.0 (95%) LOS: 12.4%
Total: 2000 W: 261 L: 288 D: 1451
2000 @ 10+0.1 th 15 exp. #8 b (now without HT on one of the testing machines, see fishcooking).
07-05-17 vd threading2 diff
ELO: -2.61 +-7.6 (95%) LOS: 25.0%
Total: 2000 W: 240 L: 255 D: 1505
2000 @ 10+0.1 th 15 exp. #8
07-05-17 vd threading2 diff
ELO: -27.74 +-10.9 (95%) LOS: 0.0%
Total: 1067 W: 105 L: 190 D: 772
2000 @ 10+0.1 th 15 threading experiment take 7
07-05-17 vd prefetch2 diff
LLR: -2.96 (-2.94,2.94) [-3.00,1.00]
Total: 40829 W: 7307 L: 7534 D: 25988
sprt @ 10+0.1 th 1 take 3
07-05-17 vd prefetch diff
LLR: -2.95 (-2.94,2.94) [-3.00,1.00]
Total: 22183 W: 3902 L: 4096 D: 14185
sprt @ 10+0.1 th 1 take 2
06-05-17 vd factorKiller diff
LLR: -2.94 (-2.94,2.94) [0.00,4.00]
Total: 19422 W: 3444 L: 3534 D: 12444
sprt @ 10+0.1 th 1 code reorg experiment
19-04-17 vd rsf diff
LLR: -2.94 (-2.94,2.94) [-3.00,1.00]
Total: 66387 W: 8385 L: 8617 D: 49385
sprt @ 60+0.6 th 1 ltc, take 3, param 585
06-05-17 vd prefetch diff
LLR: -2.95 (-2.94,2.94) [-3.00,1.00]
Total: 74178 W: 13182 L: 13464 D: 47532
sprt @ 10+0.1 th 1 verify for no regression.
06-05-17 vd thisThread diff
LLR: -2.95 (-2.94,2.94) [-3.00,1.00]
Total: 6773 W: 891 L: 1050 D: 4832
sprt @ 10+0.1 th 5 #1102 No regression 5 threads
06-05-17 vd thisThread diff
LLR: -2.95 (-2.94,2.94) [-3.00,1.00]
Total: 12053 W: 2086 L: 2263 D: 7704
sprt @ 10+0.1 th 1 test for no regression (PR #1102)
05-05-17 vd lmrCurrent diff
LLR: -2.97 (-2.94,2.94) [0.00,5.00]
Total: 6284 W: 1071 L: 1170 D: 4043
sprt @ 10+0.1 th 1 stc, take 3
05-05-17 vd toCurrent diff
LLR: -2.94 (-2.94,2.94) [0.00,5.00]
Total: 6529 W: 1122 L: 1219 D: 4188
sprt @ 10+0.1 th 1 stc, take 5
04-05-17 vd lmrCurrent diff
LLR: -2.95 (-2.94,2.94) [0.00,5.00]
Total: 39977 W: 7099 L: 7056 D: 25822
sprt @ 10+0.1 th 1 take 2
04-05-17 vd lmrCurrent diff
LLR: -2.95 (-2.94,2.94) [0.00,5.00]
Total: 37344 W: 6686 L: 6653 D: 24005
sprt @ 10+0.1 th 1 stc
04-05-17 vd toCurrent diff
LLR: -2.95 (-2.94,2.94) [0.00,5.00]
Total: 21751 W: 3942 L: 3974 D: 13835
sprt @ 10+0.1 th 1 stc, take 4
04-05-17 vd toCurrent diff
LLR: -2.96 (-2.94,2.94) [0.00,5.00]
Total: 23985 W: 4348 L: 4371 D: 15266
sprt @ 10+0.1 th 1 stc take 3
04-05-17 vd toKillers diff
LLR: -2.94 (-2.94,2.94) [0.00,5.00]
Total: 6548 W: 1142 L: 1239 D: 4167
sprt @ 10+0.1 th 1 stc take 2
04-05-17 vd toCurrent diff
LLR: -2.95 (-2.94,2.94) [0.00,5.00]
Total: 5378 W: 916 L: 1018 D: 3444
sprt @ 10+0.1 th 1 stc, take 2
04-05-17 vd toCurrent diff
LLR: -2.97 (-2.94,2.94) [0.00,5.00]
Total: 5786 W: 977 L: 1078 D: 3731
sprt @ 10+0.1 th 1 stc
03-05-17 vd toKillers diff
LLR: -2.95 (-2.94,2.94) [0.00,5.00]
Total: 3770 W: 626 L: 735 D: 2409
sprt @ 10+0.1 th 1 stc
03-05-17 vd moreKillers diff
LLR: -2.96 (-2.94,2.94) [0.00,5.00]
Total: 12599 W: 2239 L: 2311 D: 8049
sprt @ 10+0.1 th 1 stc
02-05-17 vd lmrD diff
LLR: -2.95 (-2.94,2.94) [0.00,5.00]
Total: 14128 W: 1794 L: 1866 D: 10468
sprt @ 60+0.6 th 1 ltc, take 4
02-05-17 vd lmrD diff
LLR: 2.96 (-2.94,2.94) [0.00,5.00]
Total: 31415 W: 5799 L: 5540 D: 20076
sprt @ 10+0.1 th 1 stc, take 4
30-04-17 vd lmrD diff
LLR: -2.96 (-2.94,2.94) [0.00,5.00]
Total: 50878 W: 9156 L: 9066 D: 32656
sprt @ 10+0.1 th 1 stc, take 2, param 1000 3000
30-04-17 vd lmrD diff
LLR: -2.96 (-2.94,2.94) [0.00,5.00]
Total: 20983 W: 3698 L: 3735 D: 13550
sprt @ 10+0.1 th 1 stc, take 3, param 0, 3000.
30-04-17 vd lmrD diff
LLR: -2.96 (-2.94,2.94) [0.00,5.00]
Total: 13710 W: 2444 L: 2511 D: 8755
sprt @ 10+0.1 th 1 stc (corrected logic), param 8000, 3000
27-04-17 vd threading2 diff
ELO: -3.39 +-5.8 (95%) LOS: 12.7%
Total: 4000 W: 566 L: 605 D: 2829
4000 @ 5+0.05 th 11 elo estimate v5
27-04-17 vd threading2 diff
ELO: -92.92 +-6.4 (95%) LOS: 0.0%
Total: 4000 W: 222 L: 1267 D: 2511
4000 @ 5+0.05 th 11 elo estimate v6
17-04-17 vd rsf diff
LLR: -2.96 (-2.94,2.94) [-3.00,1.00]
Total: 136547 W: 17839 L: 18167 D: 100541
sprt @ 60+0.6 th 1 ltc
26-04-17 vd killerIsBonus diff
LLR: -2.98 (-2.94,2.94) [-3.00,1.00]
Total: 37391 W: 6607 L: 6828 D: 23956
sprt @ 10+0.1 th 1 stc, alternative
26-04-17 vd ExclStat diff
LLR: -2.95 (-2.94,2.94) [0.00,5.00]
Total: 36133 W: 6538 L: 6509 D: 23086
sprt @ 10+0.1 th 1 stc, against PR1085.
26-04-17 vd moveInit diff
LLR: -2.95 (-2.94,2.94) [0.00,4.00]
Total: 28060 W: 5020 L: 5081 D: 17959
sprt @ 10+0.1 th 1 stc, as discussed in #1085 delay copy
26-04-17 vd threading2 diff
ELO: -4.17 +-5.9 (95%) LOS: 8.3%
Total: 4000 W: 578 L: 626 D: 2796
4000 @ 5+0.05 th 11 elo estimate v4
25-04-17 vd killerCopy diff
LLR: 2.96 (-2.94,2.94) [-3.00,1.00]
Total: 28368 W: 3730 L: 3619 D: 21019
sprt @ 60+0.6 th 1 ltc, test as bugfix